Design Center

BGA Breakouts and Routing
Charles Pfeil's book is very helpful for those designing PCB with BGA devices.

• Low power design for analog/mixed signal IP

• PCB Tools Vendors Reference Chart

• ESL handoff: closer than you think

• Preserving The Intent Of Timing Constraints

• Bridging the Gap Between Silicon and Software Validation

Learning Center

Most Recent Courses

• IBM is the Clear Choice for EDA Computing
  Technology course  60 min.
• Electromagnetic Noise Reduction Techniques: Part 1
  Technology course  30 min.
• Electromagnetic Noise Reduction Techniques: Part 2
  Technology course  25 min.
• Silicon Tuner Training
  Product course  50 min.
• EMC for ICs
  Technology course  2 hours 15 min.
• sVM—System Verification Methodology
  Product course  45 min.
• Migration to Linux on Intel for EDA Tools Environments
  Lecture  30 min.

Product Center

Latest Product Articles

• Synopsys announces synthesizable PowerPC cores
• Cadence introduces C-to-Silicon Compiler
• Synopsys broadens DesignWare SATA solution with Device IP
• Mentor Accelerates Verification of PCI Express Applications
• Board Interchanger for Concurrent Mechanical and PCB Design

Under the Hood

• Under the Hood: Silicon in autos driving patent plans
• Under the Hood: Inside the Apple iPhone
• Under the Hood update: Software at heart of iPhone's simplicity
• DRAM makes move to copper
• Inside Intel's 65-nm NOR flash
• 65 nm: Where are the chips?

Reference Designs

• Broadcom and Avago Technologies Announce Advanced Features and New Price Points to Drive Bluetooth® Laser Mouse Products
• Fujitsu developer kit for fingerprint identification

Technical Paper Library

Latest Technical Papers

• Reducing Physical Verification Cycle Time
• The New Wave in Functional Verification: Intelligent Testbench Automation
• Increasing Productivity With Quartus II Incremental Compilation
• Advanced Debug Methods for DSM Driven Testbenches
• Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter Using SystemVerilog Assertions
• Green Engineering—Improving the Environment and the Bottom Line
• Stator Coupling Model Analysis

Featured Technical Papers

• Using Virtual Platforms for Pre-Silicon Software Development
  Synopsys
• Clock Domain Crossing Demystified: The Second Generation Solution for CDC Verification
  Real Intent and Sunburst Design
• ZeBu: A Unified Verification Approach for Hardware Designers and Embedded Software Developers
  Emulation and Verification Engineering (EVE)
• Demystifying DO-254
  Mentor Graphics

Webinars

Upcoming Webinars

• Jul 31, 2008: 
  Achieving Optimal Performance and Low Power for SATA Device Designs
  Synopsys

Latest Webinars

• Building a VMM-Based Constrained Random Environment for Bus Protocol Verification
  Synopsys
• Co-simulation Enables Efficient Co-Design of WLAN Antenna and Circuitry
  Agilent Technologies