June 30, 2009
Design trust and verification
By Nicolas Mokhoff

It's generally acknowledged that we have entered the 45 nm processing node era. It's also well known that at this node the mantra among SoC designers should be "verify!, verify!, verify!"

IP provider Virage Logic Corp. this week announced that since being named TSMC's 40-namomenter early development partner in 2007, the company has seen strong adoption of its extensive 40nm product portfolio.

Comprising embedded SRAMS, embedded memory test and repair, logic libraries, and memory development software, the company's silicon-proven 40nm product offering has been designed to optimize area, performance, power and yield.

Virage claims that today more than ten customers rely on Virage Logic's 40nm product portfolio to design more efficient chips more quickly and with less risk as they develop products for such end markets as graphics, consumer, enterprise, networking, wireless, and handheld.

"TSMC selected Virage Logic as an early development partner at 40nm as a continuation of our collaboration in technologies ranging from 250nm to 40nm. Virage Logic and TSMC work closely to qualify IP through both Virage Logic's procedures and TSMC's procedures including silicon validation of these advanced technology IP solutions," said Dan Kochpatcharin, deputy director, IP Portfolio Marketing at TSMC. "These extensive silicon quality report results are available to designers of advanced SoCs for review when choosing Virage Logic's broad IP portfolio on TSMC's 40nm process."

That seems to settle it.

Unless you start listening to the verification guys. Rajeev Ranjan, Chief Technology Officer at Jasper Design Automation says in an upcoming EE Times Viewpoint: "What is indisputable is that all today's conventional verification tools are proving insufficient as we head toward 45nm designs; and building faster and larger compute farms and utilizing specialized hardware is not the answer. New methodologies and technology are needed, and quickly, to address the challenge."

Ranjan is pushing the technology Jasper is known for: formal verification. The company has accumulated an impressive number of patents in the formal verification field.

He claims that over time formal verification has attracted a broad audience: "Over the past five years, formal verification was deployed first by experts in the verification team, then by the entire verification team, and lately it has been spreading to the designers themselves."

He contends that formal verification can mitigate risk at several stages of the 45nm design flow.

"To check the IP block for all possible configurations, formal technology can perform analysis and also check for compatibility amongst different modes of operation. The latest formal advances can check the correctness of programming sequences used to configure the IP blocks and can also help generate efficient programming sequences from scratch," says Ranjan.

So while the system-on-ship designer can obtain the latest IP blocks from Virage Logic, verifying that the IP block will work as prescribed in the final SoC requires trust in the adopted verification tools and methodologies.

Jerry Frenkil, Sequence Design CTO, refers in another upcoming EE Times Viewpoint to his company's power verification approaches. But the mantra he applies to power verification can just as well be applied across the board to all verification design flows: Instead of using a "trust but verify" a better approach to verification is to start early and "verify, verify, verify."

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June 23, 2009
Time heals all wounds, and missteps?
By Nicolas Mokhoff

Investors are slashing through a decade of over-investments in semiconductor startups. Top venture capitalists say the costs of bringing a new processor or system-on-chip to market are becoming prohibitive. Raising new funds to invest in high tech companies of any kind is getting increasingly difficult.

That's the grim news from Silicon Valley where EE Times editor at large Rick Merritt filed this story.

Increasingly only the few big chip makers will be able to afford to design big SoCs: Tape out costs can run as high as $20 million, but they are dwarfed by verification costs that can soar five times as high, according to venture capitalist Andy Rappoport, who contends that the payroll for verification teams alone can cost $2 million a month and silicon support teams to serve a couple OEM customers can run another million per month.

Mark Stevens, a principal at Sequoia Capital has been studying a model used in the biotech industry. Big companies help fund startups and once their products are ready to go they buy up the companies outright in what amounts to pre-arranged marriages.

I wonder if this model can be applied to large EDA companies. That is, fund a startup, and then buy it out. Has it been done before?

Some out of the box thinking needs to be contemplated. The EDA industry is hurting and nimble new players need to give the large players a run for their money.

One such company might be around the corner.

Oasys Design Systems, coming out of stealth mode after Independence Day, is claiming to reinvent RTL synthesis for chips beyond 20-million gates. The company has assembled a board of diectors that includes Joe Costello, former CEO of Cadence Design Systems, Sanjiv Kaul, former Sr. VP and GM of Synopsys, and Larry Yoshida, former CEO of Innotech and Tokyo Electron.

"When I learned of the Oasys approach to a significant problem, I saw real invention again. I had to get involved," is the story line offered by Costello who once expressed his angst about VCs and EDA.

Time will tell.

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June 16, 2009
Virtual platforms, research & venture capital
By Nicolas Mokhoff

DAC this year has its work cut out for it. The recession has hit the EDA industry hard and every player is being frugal in evaluating expenditures. Nevertheless the organizers of the 46th annual conference and exhibits will make the best of it.

This year DAC is offering a new workshop on Virtual Platforms as a way to bridge the gap between hardware and software developers. Presenters representing user, IP developer and EDA tool vendor will explore timing mechanisms in TLM (Transaction-Level Modeling), integration of RTL Models into Virtual Platforms for complex multicore systems, and platform composition and refinement.

Industry experts will share their experiences in software functional verification, architectural exploration on VPs, combining TLM-2.0 code with legacy virtual platforms, and system verification.

Speakers include experts from Cadence Design Systems, Carbon Design Systems, CoWare, EVE, GreenSocs, Imperas, Intel, Open Virtual Platforms, Posedge Software, Qualcomm, and Synopsys.

You can register for the Wednesday, July 29 all day workshop.

The day before at noon you can partake in the IEEE Council on Electronic Design Automation (CEDA) where Jeannette M. Wing, assistant director of the National Science Foundation (NSF), will speak on the "Frontiers in Research and Education in Computing: A View from the NSF."

Wing is assistant director of NSF Computer and Information Science and Engineering Directorate (CISE), an organization that funds 84 percent of all academic computer science research in the United States. Wing is also the President's Professor of Computer Science in the Computer Science Department at Carnegie Mellon University.

The lunch is open to all DAC attendees on a first-come, first-served basis.

Alternatively, take in the "Town Hall Meeting: Can We Afford for Start-Ups to Wind Down?", chaired by venture capitalist Lucio Lanza who will have speakers from Intel Capital, Needham & Company, and Denali Software consider the long-term health of the semiconductor industry.

The only thing standing in your way now is your boss' OK to travel to San Fran last week of July.

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June 09, 2009
EDA industry riding on own waves
By Nicolas Mokhoff

The EDA industry is making waves but the waves are not reaching the business shores. Both encouraging news about funding and discouraging news about consolidation keep the EDA industry in constant state of bobbing.

On the one hand start-up Copenhagen-based Teklatech has completed a $1 million round of funding from a group of private investors in syndication with a major Scandinavian venture fund.

On the other hand industry watcher Sramana Mitra sees some consolidation in the failing EDA industry, which she said has not reached the proportions that she would like to see, "but at least it's a start."

Her conclusion: "The EDA industry looks very precarious, and other than Synopsys, the other 3 major players look wobbly at best. If they continue to resist the inevitable consolidation that I have been calling for over the last 3 years, the level of misery in store is just sordid."

Gary Smith of GarySmith EDA, an analysis firm, in his latest Note on the attendance at the recent DATE 2009 in Munich, laments how EDA industry players are short-sighted as a whole.

He warns his readers to "keep in mind most of your customers of tomorrow are not your customers of today."

The recesssion has kept many EDA participants at bay, but thinking long-term is still a good idea for when the economy recovers. The sun always comes out after a rainstrom.

If you had to miss DATE in Munich, you still have time to make plans to attend DAC 2009 in San Francisco end of July. I recommend getting a C-level view of EDA during DAC's Management Day.

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