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Featured Design Center |
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Multi-Core -- A New Challenge for Debugging
Development of complex systems with powerful hardware on one side and ambitious applications on the other side, benefits from on system-spanning on-chip support for debugging.
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Analog/Mixed-Signal Design
Low power design for analog/mixed signal IP
Power reduction and management techniques using multiple clock and power domains, dynamic voltage and frequency scaling and power gating are effective for digital circuits but for analog design, lowering power consumption must be considered early in the design phase.
Dynamic Voltage Droops & Total Power Integrity
This article sheds light on key differences such as voltage droops and noise wave propagation resulting from on-chip load interaction with power network impedance and discusses how total power integrity may be rigorously inspected through rapid analyses and physics-based simulations.
Characterizing Nanometer CMOS PLLs, Sigma-Delta ADCs and AGCs
The verification of analog/RF blocks presents challenges when using a digital fastSPICE simulator. The use of an analog fastSPICE simulator mitigates them.
See all Analog/Mixed-Signal Design »
Board-Level Design
Viewpoint: Package-on-package is killer app for handsets
To continue Moore's Law trend toward smaller, sleeker handset devices, designers can leverage advanced packaging and interconnect methods to meet the miniaturization requirements.
BGA Breakouts and Routing
Charles Pfeil's book is very helpful for those designing PCB with BGA devices.
Silicon is only the beginning
Choosing the right package during the creation of a chip for the test phase of development and for the final device can not only reduce your time-to-market but also help you create tangible benefits for your customers.
See all Board-Level Design »
Electronic System Level (ESL) Design
Algorithmic synthesis improves designers' efficiency
Algorithmic synthesis moves the creation of application engines (algorithms on silicon) to a higher level of abstraction, giving significant time and cost savings.
Power trends point to a knowledge of integration
As a holistic, system-level view of power management -- in addition to ever-advancing chip technologies -- becomes increasingly important, open conversations and collaboration among DSP, SoC, MCU and analog power management designers are critical, write three managers from Texas Instruments.
ESL handoff: closer than you think
Any viable design methodology requires tight links to implementation, and to meet this need a new generation of High-Level Synthesis tools is emerging, based on SystemC.
See all Electronic System Level (ESL) Design »
Digital IC Design
Reducing Power Consumption in a Fiber Channel Switch
Reducing power early in the RTL design process has a positive ripple effect throughout the entire system. It makes achieve timing closure easier. It simplifies packaging, lowers system costs and influences the product form factor.
Capturing and communicating power-efficient design knowledge
A low-power kit gathers expert knowledge and best practices to: eliminate common problems; establish flows to ensure tools and technologies are applied to achieve the best results; and establish processes to ensure predictability.
In-system programming of FLASH via control unit application
A high level of data integrity and data security is essential when using FLASH memory in automotive control units. In order to successfully implement FLASH solutions in this kind of environments it takes to consider a set of basic rules.
See all Digital IC Design »
Verification
Multi-Core -- A New Challenge for Debugging
Development of complex systems with powerful hardware on one side and ambitious applications on the other side, benefits from on system-spanning on-chip support for debugging.
The need to address power during manufacturing test
Until recently, the idea of managing power during manufacturing test has been a secondary concern. But with shrinking geometries and lower voltage thresholds comes an increasing awareness that excessive power consumption during test can have an impact on digital IC reliability.
Learning not to fear PCI Express compliance
Verification of a PCI Express implementation using a third party VIP proves successful.
See all Verification »
See all Design Center »
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About the EDA DesignLine How-To Section
About the EDA SesignLine How-To Section
The EDA DesignLine How-To section delivers engineering articles focused on EDA tools; ESL design; verification; DFM; signal integrity; chip designs at 45, 65, and 90 nm, board layout, and system level design.
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