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Featured Design Center |
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A silicon-proven interoperable PDK
In 2009, TSMC announced the availability of the industry's first interoperable process design kit (iPDK). An iPDK benefits the entire TSMC design chain. TSMC customers will be able to use one unified iPDK to provide advanced functionality across multiple EDA vendor tools, improve design accuracy, shorten design cycle times, and promote design reuse.
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Analog/Mixed-Signal Design
PRODUCT HOW-TO: Efficient Fixed-Point Implementation of the Goertzel Algorithm on a Blackfin DSP
How to use the Goertzel algorithm flow and its fixed-point implementation on the Analog Devices Blackfin BF5xx processor its special arithmetic modes as well as how to efficiently implement 16.16 fixed-point multiplications.
JFET applications in today's analog world
Understand how this basic device fills a vital circuit function
A mixed signal approach to debugging DDR DRAM interfaces
This article highlights a few of the many challenges to using the new generation of DDR3 and LPDDR DRAMs in embedded systems and how intelligent use of a mixed-signal oscilloscope (MSO) can overcome them.
See all Analog/Mixed-Signal Design »
Board-Level Design
Ensuring the thermal integrity of your IC package/PC board design
Some basic tests will verify your PCB/IC thermal modeling and reality
Easing the challenge of RF design (Part 2 of 2)
Designing in a wireless link need not be a nightmare--if you follow some simple guidelines
Understanding Factors Affecting Intel QuickPath Interconnect Signal Integrity (Part 2 of 2)
This article explores and explains key issues related to signal integrity in this interconnect scheme, as well as other parallel and serial differential bus designs
See all Board-Level Design »
Electronic System Level (ESL) Design
Embedded system virtualization for executable specifications and use case modeling
To reduce the time-to-market of embedded system projects, virtual hardware platforms offer a method to develop hardware-dependent software and application software before production hardware is available. However, for true system-level specification and architecture optimization, full-system virtualization is required, including abstract models of HW, behavioral models of application SW and use cases.
Low power LDPC decoder created using high level synthesis
This article gives an example in which an HLS tool is used, together with architectural innovation, to create a low power LDPC decoder.
Book excerpt: 'Project management of complex and embedded systems'
The management of automotive design projects provides a window into how to handle other complex development and manufacturing efforts.
See all Electronic System Level (ESL) Design »
Digital IC Design
Building better memory management for high performance wired/wireless networks: Part 2
The authors evaluate the performance of variable- versus fixed-size memory pools in tests implementing the two approaches for LTE and WiMAX protocol stacks
Building better memory management for high performance wired/wireless networks: Part 1
The authors describe a variable pool memory management scheme that has been implemented for LTE and WiMAX protocol stacks and has exhibited excellent performance, especially when compared to traditional fixed-pool implementations.
A silicon-proven interoperable PDK
In 2009, TSMC announced the availability of the industry's first interoperable process design kit (iPDK). An iPDK benefits the entire TSMC design chain. TSMC customers will be able to use one unified iPDK to provide advanced functionality across multiple EDA vendor tools, improve design accuracy, shorten design cycle times, and promote design reuse.
See all Digital IC Design »
Verification
High-level synthesis, verification and language
The preferred high-level design methodology proceeds from high-level code to RTL code. Good verification practice requires that the input to High-level Synthesis (HLS) be verified first, via simulation (or some other analytical means), and then the output of HLS be verified, again via simulation or some other means. Using SystemC as the input language to HLS enables this flow, but using C as the HLS input language imposes a serious limitation on doing verification this way.
Facilitating at-speed test at the register transfer level
This white paper discusses at-speed testing challenges and discusses a solution for facilitating at-speed test at the register-transfer level.
Guidelines for complex SoC verification
As verification takes up a significant part of the design cycle, planning, managing the project dynamics and a metrics-driven execution will be of much help says the author, a senior ASIC engineer
See all Verification »
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About the EDA DesignLine How-To Section
About the EDA SesignLine How-To Section
The EDA DesignLine How-To section delivers engineering articles focused on EDA tools; ESL design; verification; DFM; signal integrity; chip designs at 45, 65, and 90 nm, board layout, and system level design.
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