Introduction
Copper interconnect was introduced to the mainstream at 130nm because of its significant advantages compared to aluminum, such as reduction in resistivity and power consumption and resistance to electromigration. Together with its advantages, copper interconnect also brought challenges to achieving high yield due to effects such as dishing, dielectric erosion and thickness variations caused by Chemical Mechanical Polishing (CMP) during planarization.
To account for copper's side effects, physical design tools insert dummy metal patterns, called metal fill, so that designs meet the required metal density " as specified by foundries " to reduce the thickness variation. However, at 65nm and below, meeting the density target does not always achieve minimum metal thickness variation, as the copper topography is affected by several layout and process parameters. An example is illustrated in Figure 1.
1. Areas of the layout with same density have different thickness due to different layout patterns.
To adequately control thickness at advanced technology nodes, new techniques are necessary to take into account not only the metal density but also the metal thickness itself.
Poor metal planarization leads to yield loss
Because the material properties of copper are different than aluminum, copper demands a different style of processing. In the aluminum process the metal is deposited and then etched to create the interconnect lines. An additional step of inter-layer dielectric (ILD) deposition ensures the isolation of the interconnect lines, and is followed by the planarization step. The copper manufacturing process differs significantly. First, the patterns are etched into the ILD, and then the copper is deposited into the trenches. As a final step, the excess copper is polished away by CMP during planarization [1].
Copper dishing, dielectric erosion, and multi-layer cumulative topography variations are side effects of copper interconnect caused by CMP, and they all adversely impact functional and parametric yield. For instance, when the copper is not totally removed from the top of the dielectric layers, a circuit short occurs. On the other hand, if the copper in the trench is over-polished, a circuit open occurs. Such variations can lead to increased variability in timing because of the increased interconnect resistance. Excess timing variability affects the operating frequency of the chip, or can cause internal timing violations impacting the functionality of the chip. The variation can also cause defocus issues in the lithography process following CMP.
The amount of variation in metal line thickness depends on the patterns themselves. The different layout patterns are characterized by layout density, layout perimeters, and line width [2]. As the polishing pad removes excess copper material, it also inadvertently removes material from the signal or power lines. CMP effects for different line and space combinations are illustrated in Figure 2.
2. Top-down and cross sectional representation illustrate the effects of CMP on metal patterns with varying width and spacing [3].
At 130nm, the use of the density-driven rule-based metal fill approach to meet foundry metal density target requirements, delivered a flat planarized surface for each metal layer. But today's advanced nanometer designs — with their increased complexity and integration — are more sensitive to copper CMP effects and, as shown earlier in Figure 1, layout patterns that have the same density do not always have the same metal thickness. To improve functional and parametric yield, a new methodology is required that addresses these CMP challenges during physical design and thus increases yield.
A new approach for optimal planarization: Model-based metal fill
It is important for the new approach not to have the limitations of the rule-based method, which considers only the foundry metal density target. The goal should be to minimize the thickness variation. To achieve this both the deposition (electrochemical plating -ECP) and CMP process profiles should be taken into account. In addition layout parameters other than density influence the deposition profile and the final topography. The new approach is a model-based metal fill method and the complete optimization flow for optimal thickness variation is illustrated in Figure 3.
3. CMP optimization flow consists of four steps.
There are three steps in the optimization flow. First, an analysis step simulates the cumulative effects of ECP and CMP on the design. Second, the areas with high thickness variation, called hotspots, are identified. Third, model-based metal fill is applied to reduce the thickness variation. Also, an additional simulation step that generates the final thickness variation map can be included for final validation.
The optimization flow shown in Figure 3 is in the process of being incorporated in Synopsys yield analysis tool suite and physical design tools. Following is a detailed explanation of each step in the flow, which has been validated in a joint project between Synopsys and the Semiconductor Technology Academic Research Center, STARC, a research consortium that contributes to the growth of the Japanese semiconductor industry by developing leading-edge SoC design technologies.
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