Introduction
It is no longer a mystery for designers and manufacturers of 45nm chips that higher process variability negatively impacts design performance, predictability and parametric yield. Manufacturing and process variations result in physical changes in devices and interconnect leading to deviations in their electrical behavior. Essentially, "what you design is not what you get" in the manufactured silicon and this manifests itself as electrical variability.
Figure 1 illustrates increased delay variability as minimum dimensions are approached and different layout styles are used.
1. Delay variability increases as dimensions decrease.
What good is it to migrate to a smaller geometry if the advantages of doing so, in terms of die size, performance, power and predictability, are lost due to increased design margins or parametric yield loss? This article outlines an end-to-end flow from parametric characterization, modeling to design analysis, optimization and final signoff. It offers a methodology for 45nm design that minimizes the impact of potential systematic (lithography, chemical mechanical planarization) and random variations.
Managing Variability Necessitates a "Statistical" Flow
Mainstream timing analysis uses a deterministic or corner-based approach to handle variability, both resulting in over-design. Another alternative to the multi-corner approach is to account for affects of process variation holistically for device and interconnect parameters achieved by using SSTA. Instead of using a pre-determined corner, SSTA accurately determines the combination of device and interconnect parameters that make for the worst outcome and factors in the probability of that outcome occurring in silicon. This makes for a better prediction of how variability will affect each design specifically with less pessimism by targeting a slightly lower probability. Since SSTA is process intelligent and sensitive to how the process data is compiled, it is important to analyze process data and create models with SSTA in mind.
2. A Statistical Flow.
If statistical analysis mitigates the impact of process variability at the design level, and the fab generates large volumes of data, weak links in the statistical supply chain are data gathering and variability modeling driven by the design flow. By targeting a specific injection point in the design flow, statistical process characterization that we refer to as DesignAware and statistical modeling techniques that we call ProcessIntelligent can be used employed. They are used to build more comprehensive and accurate models for statistical timing analysis.
Figure 2 shows an example of a statistical flow that results in a more integrated statistical flow from fab to design and back to fab that is necessary for optimizing design in the presence of variability.
How Variability is handled today
One of the challenges the industry faces is that building a robust 45nm process model requires closer cooperation between design teams and the fab. The design-side needs to provide adequate design information and EDA tool expectations to the fab, so that the fab can build a model suitable for the upstream design flow. Similarly, the fab needs to provide a model in the designer's language in terms of electrical parameters. The designer doesn't really know or care about what slurry the fab uses or by how much the dopants are varying. At most, the designer cares about ensuring that variability in threshold voltage, transistor length or metal parasitic variations are correctly modeled and captured during library characterization.
To-date, fabs collect a small sample of within-die data, a large sample of aggregated die-to-die, wafer-to-wafer data, without regard to correlation which is important for the upstream statistical design flow. Further mainstream modeling involves taking that data along with sensitivity-based device simulations to build a deterministic or statistical model.
For example, the fab builds a testchip containing a vernier of test structures designed to elicit electrical parameter variations such as Vt, Ion, Ioff, R, C. Depending on the front-end (transistors) or back-end (interconnect) characterization, the raw data is collected and then fed into either a SPICE parameter extraction tool or a parasitic extraction tool. Both of these flows are in their early phases of evolution toward a statistical flow and accuracy of each is limited by the many underlying model assumptions.
Figure 3 illustrates that deterministic or corner based methodologies result in large design margins or parametric yield fallout, both of which are undesirable.
3. Result of a deterministic or corner-based methodology.
Timing Analysis Requirements
Modeling process variation in SSTA is achieved by enhancing the traditional delay and RC (resistance and capacitance) models to include sensitivities to process parameters. For example, the Statistical ECSM (effective current source model) format is an enhanced version of the nominal PVT (process, voltage, temperature) library. This library is used to model how sensitive the delay of a device is to variation of process parameters such as oxide thickness or gate length.
The timing analysis solution can then use this sensitivity information in conjunction with the statistical parameter distribution information to provide a delay probability distribution for a particular path or block.
Statistical delay models such as S-ECSM are generated by varying the individual parameters of the all the transistor models in a standard cell to determine what effect a change will have on delay. Transistor models and probability distributions for their parameters should be derived from silicon measurement data with SSTA in mind in order to enhance the accuracy and completeness of the flow.
SSTA-driven Process Data Gathering
When it comes to collecting data for statistical timing, more is not necessarily good. What is needed from a process characterization framework is a DesignAware data set that:
- Incorporates a large sample of within-die physical parameter variations
- Includes fine-grained vernier for each physical parameter
- Supports a large number of contextual dependencies
- Has designed-in features for separating root causes of yield fallout
- Delivers high-resolution electrical data suitable for statistical model development
4. An example of data gathering at the wafer level.
Figure 4 shows an example of such data gathering at the wafer level (WL), die level (DL) and block level or within-die (BL). Here-in devices with similar architectures are placed at varying distances on silicon. Measurements from the set of devices are analyzed.
5. Extraction of correlation among blocks.
Figure 5 shows how correlation is extracted from both neighboring devices and devices far apart. Note that the same colored blocks imply the same device architecture and different colors imply different architectures.
Is gathering such data enough? No, not for supporting the needs of advanced statistical analysis. Data simply provides awareness not intelligence. The next step is to take this data and mold it into statistical models we call ProcessIntelligent that separate types and sources of variations in a manner suitable to statistical timing analysis. Such treatment to raw process data is critical to improving accuracy of design analysis.
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