Introduction
In July 2006, the Accellera board approved a revision VHDL standard (revision 1076-2006-D3.0) put forward by the Accellera VHDL Technical Subcommittee (VHDL TSC). As an Accellera standard, revision 1076-2006-D3.0 is ready for industry adoption.
This standard was a tag-team effort between the IEEE and Accellera committees. Work on this standard started as the IEEE VHDL Analysis and Standardization Group's (VASG) VHDL-200X effort in early 2003. The VHDL-200X team made great technical progress, however, it failed to find a funding model to fund the LRM editing.
In June 2005, the VASG transitioned the work to the Accellera VHDL TSC. The Accellera VHDL TSC merged the VHDL-200X proposals with additional items submitted by Accellera VHDL TSC members. It then prioritized the proposals based on user input ensuring that proposals selected for the standard are what the user community wants. It then did super-human work to finalize the standard and funded the LRM editing.
An abbreviated list of changes includes:
- PSL directly in VHDL code
- Packages and subprograms with generics
- Formal Generic Types, Subprograms, and Packages
- Fixed and floating point packages
- Composite types (records & arrays) with elements that are unconstrained arrays (facilitates creation of matrix types)
- Hierarchical signal reference
- Simplified sensitivity lists using process(all)
- Simplified conditionals (if, ...)
- Simplified case statements
- IP protection mechanisms
This article provides an overview of the updates included as part of Accellera 1076-2006-D3.0.
Integration of PSL
Assertions are a concise way to specify static and dynamic (sequences of events) conditions. They can be used to specify design and interface requirements that must or must not happen. They can be checked either dynamically during simulation or statically using formal verification techniques. By validating their conditions with the design, they add visibility into the design's internal state.
Rather than develop a VHDL specific syntax for assertions, IEEE P1850 Property Specification Language (PSL) has been integrated into VHDL. As a result, PSL vunits (vunit, vmode, and vprop) become VHDL primary units and may include a context clause prior to the vunit. PSL declarations may be put into packages, and the declarative part of an entity, architecture, or block statement. PSL directives (assert and cover) become VHDL statements and are permitted in any concurrent statement part.
By integrating PSL, VHDL leverages a standard assertion language that can be used with other HDLs and verification languages and at the same time has the same capabilities offered by a custom assertion language like SystemVerilog assertions (SVA).
Type Generics & Generics on Packages
To increase opportunities for re-use, generics have been extended. Types, subprograms, and packages can now be passed as generics. Packages and subprograms can now have a generic clause. A generic may now reference a previously declared generic. The following shows a generic package with formal type generics.
A generic package or subprogram must be instantiated before it can be referenced or used. The following package instantiation creates a package with overloading for Mux4 and the type std_logic_vector. Additional instances can be created for other types. To use these package instances, they must be referenced with a use clause (such as use work.MuxPkg_slv.all ; ).
While this example showed extended generics being used for RTL design, there are also numerous opportunities to use generic packages for verification " such as creating generic packages for creating data structures.
Hierarchical Reference
Hierarchical references have been added to allow an entity (such as a testbench) to probe and force signals that are defined in another part of the design hierarchy. The hierarchical reference allows objects (signal, shared variable, or constant) to be accessed by specifying a path to the object. The example below shows an object being directly forced using a relative path. Note that while the type must be specified, the range constraint for an array type (such as std_logic_vector) is not required.
A <= <>;
In addition, the capability to force a signal to a particular value has been added. A force ignores any signal resolution and sets the value to the specified value. Forced values can be removed using release. Note that normal driver resolution will occur in blocks hierarchically above the block with the forced signal. Forcing an in port and signals forces the effective value. Forcing an out or inout forces the driving value. The example below uses an alias to create a short hand name for a hierarchical reference and then forces different values on the signal and finally releases the value.
Composites with Unconstrained Arrays
Composites have been extended to allow arrays and records to contain unconstrained arrays. One use of this is to create a matrix type (such as std_logic_matrix shown below). This allows ports and signals to be declared of this type and the size specification deferred until the object is declared.
Fixed Point Packages
A new package that defines fixed point math has been added. The new package, ieee.fixed_pkg_generic, defines the types ufixed and sfixed. To support fractional parts, negative indices are used. The range downto is required. The whole number is on the left and includes the zero index. The fractional part is to the right of the zero index.
A ufixed (or sfixed) addition/subtraction operation has a full precision result (unlike numeric_std which does modulo addition/subtraction " result is the same size as the largest array operand).
Floating Point Packages
A new package that defines floating-point math has been added. The new package, ieee.float_pkg_generic, defines the type float. The range downto is required. The sign bit is the left most bit. The exponent contains the remaining bits on the left downto and including the zero index. The mantissa (fractional part) is to the right of the zero index.
This example only shows a portion of the floating point capability. For more on the fixed and floating point packages are available in the papers at http://www.synthworks.com/papers.
Stop and Finish
The capability to stop a simulation with calls to procedures stop or finish has been added. The procedures stop and finish are bound to VHPI internal procedures.
Context Unit
A new primary unit, called a context unit, has been added. A context unit is a named primary unit that allows groups of library, use clauses, and other context units to be referenced by a single name. An example of a context unit is shown below.
Rather than being overwhelmed by a large group of package references, a design unit can now reference a group of packages by referencing a single context unit as follows.
context work.IEEE_CTX ;
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