Introduction
As the complexity of electronic designs continues to increase, the challenge of verifying their functional correctness is increasing as well. The problem is compounded with the increasing market demands to deliver the next more complex version of product in even lesser time and with tighter cost constraints. Under these circumstances, ensuring the functional correctness of the modern devices in given time can not be satisfactorily achieved by simply scaling up the verification resources using the traditional techniques. This makes it absolutely necessary for the companies that provide verification solutions ("the EDA verification companies") to deliver new products & techniques to do the verification tasks.
In this article the challenges faced in verifying today's complex designs are discussed. Along with, the corresponding advancements required in verification products and techniques to overcome these issues have been suggested. In a way, this article provides an insight of today's verification problems faced by semiconductor companies and also suggests what should be considered in the verification platforms to overcome these challenges.
Multi-language environment
All modern design and verification environments involve multiple languages. This is an irreversible trend that will continue in future. This is a bold statement to make these days when the electronics community is high on SystemVerilog language " one language considered to have the potential of meeting all design and verification needs. In fact, all major players have delivered a solution and methodology around it.
The basic premise of my statement is that today all designs and their verification environments depend on some external models or intellectual property which comes from a different group or company. It is not possible today to start a new design or verification environment from scratch. Now, there is no or little control over the language and modeling style used in such several external models that are an integral part of the complete system. The other important reason for environments to remain multi-language is the large amount of existing code that has been working for many years and is a critical part of the design or verification environment. This will probably never go away as it will never be considered worth to invest in moving away from code that is well-proven in many projects.
Overall, with due respect to all existing and new languages, there are several practical reasons to believe that modern designs will continue to involve multiple languages. If not at block or sub-system level, it's generally true at full system level or can always happen in the future - next generation of the design.
By the way, having multi-languages in the design and verification environments is not a problem. In fact every standard language has it's own advantages and is suited for certain aspects " Verilog for RTL and gate level, VHDL for rich data types and better structured constructs, SystemC for high level modeling, e for advanced verification, SystemVerilog for assertions, coverage and advanced verification. So it may be more efficient to have multi language environment by choosing the best language for different aspects.
The actual problem is that the current verification tools either do not support all languages or do not support them well. So beware if the verification platform vendor is giving an argument which in reality is an excuse for its inability to support or invest in all industry standard languages.
It should be seen that the verification platform is supporting all prevalent and upcoming languages. What becomes equally important is to provide a good interoperability among the existing and emerging languages. With an increasing inter-dependency on external partners to meet today's requirements, it is important to go with solutions that support and strictly adhere to standards and LRMs of all industry accepted languages and advocates a methodology which is language independent, is open, interoperable and works across tools.
Better predictability
It is obvious that any non-trivial activity requires a certain amount of planning to complete it in time and with a high degree of confidence. There is a high risk of failure in activities where there is no proper advance planning or progress tracking during execution. At least such tasks can not be completed with desired quality and satisfaction. Now, the complexity of the task determines when to start the planning, who all should be involved, what will be the success criteria, how the progress will be tracked and measured. For example " a weekend getaway can be planned during the week with a couple of friends, whereas a company-wide event needs a month long planning involving event organizers and financiers. The functional verification of modern designs is certainly much more complex than these examples. It means that the planning of verifying the design should start from the specification stage itself and it should involve all key stakeholders.
The other key ingredient of predictability is the ability to measure the progress during the course of activity. Imagine the confused state of a long distance runner who is running on a track with no milestones. During the race, he does not know should he accelerate now or continue running at constant pace for some more time as he does not know how far the finish line is. Similarly, in functional verification it is extremely important to keep measuring that time in spend in right activities in order to make the most of the available verification resources. Moreover, increasing efforts in critical tasks that are lacking should be realized and acted upon in-time.
The verification platform you choose should have the ability to easily capture the scope of the verification problem and measure the progress during the complete project. It must provide tools that let you specify these goals in the beginning of the project that are considered necessary to achieve for ensuring functional correctness of the design. There should be a metric that can be used to track and measure the progress during the entire project. Coverage is a standard metric in functional verification of designs. However the users generate various kinds of coverage like code, functional, assertion. As a result, to get the complete picture of the progress, the verification platform should also have a common mechanism to read, write, view and analyze the various kind of coverage that the user can generate. It can only then provide the right tracking and measurement of overall verification progress. As a result, gives more accurate prediction of meeting the verification goals in time.
Scalability to design complexity
It is expected that the efforts to verify the subsequent variants of the design will not be similar to the original version. It can be ensured when the majority of the verification environment is re-useable in the future so that the time & effort are a fraction of what was spend on the original version.
Scalability is not only important across versions but also within a particular version of the design. The bulk of verification happens by simulating the design with various test benches. However, the verification can be started as early as the architects define the design specification and the designers start designing at the block level " even when the test bench or verification environment has not been created. This is possible by expressing the intent in the form of assertions and verifying those using formal techniques. Similarly, in the end, when all components are brought together for full system level verification, hardware acceleration is often necessary as simulation can not handle due to performance reasons. As the design matures and scales up from different blocks level to fully integrated system, the verification platform should be able to scale accordingly and should continue to find bugs at all times.
Last but not the least, the debugging environment for the engineers should remain uniform, preferably supported natively in the verification platform. There are many more important tasks to be performed than learning and getting used to a new debugging environment.
The verification environment should be able to scale-up with the increasing complexity of future designs. The methodology should encourage the principle of re-usability of code. The verification platform include tools that allows the user do verification for maximum possible time of the design cycle " starting early with assertion based verification to the final complete system verification using acceleration on demand. The simulation platform should be able to offer easy interoperability with such alternate verification techniques like formal verification and hardware accelerator. Finally, the verification platform should have a unified debugging environment for all different languages.
Summary
The functional verification of designs is getting more and more difficult. EDA vendors are challenged to deliver the means to achieve 'in-time' closure of verification of modern complex designs. The verification platform should deliver not just faster simulator engines, but also provide support for all prevalent languages; an open & interoperable methodology, along with the verification automation tools to simplify the verification process. It should include tools for managing and tracking the verification progress of functional correctness of today's complex designs.
The verification platform should have the tools and methodology that encourages re-usability. It has complete set of tools to ensure that the verification scale-up to the design complexity to handle not only the current design but also the next more complex versions.
We discussed several critical functional verification requirements of modern complex designs. The verification platform that addresses all or most of them will be able to live up to the challenge of ensuring the functional correctness of current and future devices with desired quality. The verification platform that puts focus on all these aspects is the right choice and will be a winner.
About the Author:
Amit Dua is Senior Product Engineer in Cadence Verification Division. He
holds a Bachelors of Technology degree in Electronics Engineering from the Institute of Technology BHU, India. He can be reached at
adua@cadence.com.
|
