Roof Planning, Rooms and Walls in SoC's
We have heard so much about floor planning for integrated circuits – routing, timing awareness, and even leakage and temperature awareness; how often do we come across the term Roof Planning in SoC's? Yet, just as the foundation of any integrated circuit is its substrate, the roof that ensures that the various functional blocks perform as required is its power grid and power delivery system.
While much attention has been focused upon the substrate through investigations of substrate noise conduction, little has been done on power grid and power delivery analysis other than the simple exercise of determining i • r drop that is substituted for comprehensive power integrity investigation. As integration continues in accordance with Moore's Law, and nanoscale SoC's include ever more functional blocks operating with switching edge rates of fast fabrication processes capable of multi-GHz operating frequencies, on-chip noise now includes significant L • di/dt content, or dynamic noise, propagated across the chip by the roof above that has two orders of magnitude lower resistivity or impedance as compared with the foundation below.
How does one decide what is the girder width of such roofs, optimizing metal usage? How does one determine how best to position the rooms of this integrated mansion so as to minimize total noise? How does one determine how best to place minimal walls of isolating decoupling capacitors so as to protect sensitive rooms from the din created by the entire system? How does one determine how low must the roof be, so as to minimize power consumption that is quadratically (active power) and exponentially (leakage) dependent upon the roof height or the operating supply voltage? This article details how these challenges may be effectively addressed in SoC floor planning.
Low power and the dominant design constraint
Extreme performance and frequency are no longer dominant design goals for SoC's. Recent years have witnessed changes in microprocessors' architectures, with multi-GHz unicore CPU devices abandoned in favor of low-frequency multi-core variants, and frequency becoming a forgotten memory. SoC's are also treading into the Ghz domain, but cautiously; great care is taken to ensure that a single dominant design constraint is not violated under any operational condition.
So what is this most sacred aspect? It is the one exponential that has hit a wall for integrated circuits of all varieties " Power. While scaling of transistor dimensions and the corresponding number of transistors per unit area continues along its 'Moore's Law' exponential for the next decade, power, which used to double roughly every 36 months for microprocessors of a specific architecture, can no longer do so. Power is the single dominant design constraint for SoC's today.
1. The exponential that hit a wall: Power.
Not Frequency, but Voltage
Low power design is a key quality measure for any ASIC or SoC today. Minimizing active power may be accomplished simply by reducing the frequency of operation in CMOS IC's, since active power is proportional to frequency. But that does not benefit most systems, since it is energy that is the principal concern. Energy consumed directly relates to battery life in portables and handheld devices where a majority of SoC's are found today.
Energy is Power • Time, and therefore lowering frequency, while reducing power, does not reduce energy used since the same task now takes more time for execution. Additionally, leakage, or static, wasted power consumption in CMOS is now about the same as active power, and it is minimally influenced, if at all, by the frequency at which a block is operated. The longer the block remains operational, more is the leakage static power consumed, and therefore more is the energy wasted. Hence the solution to minimizing energy consumption IS NOT reducing FREQUENCY, but IS reducing the VOLTAGE at which the SoC is operated, since both active and leakage power are strongly dependent upon operating voltage. Nanoscale CMOS processes offer an interesting opportunity in being able to reduce operating voltage while still maintaining the necessary frequency of operation [1] because of the near linear relationship of transistor saturation drive current to the applied control voltage.
Bringing the roof down: analysis complexity hits a wall
Reducing and optimizing operating voltage levels needs to be done with full cognizance of required chip performance and necessary noise margin. Simply put, operating voltage must be high enough that even with anticipated reduction due to on-chip noise, the chip and its functional blocks perform as specified under all process and voltage variations. At the same time, the operating supply differential must be the lowest that it can be made, while ensuring that critical pathways in high-performance blocks see minimal reduction in supply differential at all times. In other words, it is essential to have spatial and temporal awareness of true dynamic noise in the chip power grid. This is where currently available tools for power integrity face difficulties in providing rapid answers.
We believe the inability of current tools in providing sophisticated power integrity information rapidly stems in large part from how circuits are physically represented within tools, in the form of polygons. Polygons do not allow us to take advantage of any of the abstract aspects of physical layout that greatly simplify electrical analysis. Whereas finite element analysis takes specific advantage of this method, through representation of arbitrary shapes as being constituted by triangular or polygonal shaped structures, such methods require enormous computing resources in order to evaluate even static variations, much less their dynamic progression.
As chips move into the nanoscale regime, the complexity of the analysis, with objects to be analyzed represented as polygons, explodes exponentially and also hits a wall. Hence tools that deal with physical objects on an integrated circuit as polygons resign themselves to doing justice to simple power integrity analyses such as i • r drop simulations.
Simplifying and speeding up analysis while improving accuracy
On the other hand, it is possible to take maximum advantage of the 'differential', 'symmetric' and 'periodic' nature of power grid design on an integrated circuit. In other words, one can comprehend both the physical aspect of power grid wires (and functional blocks and decoupling capacitance) as well as their principal electrical and architectural characteristics and employ these aspects into simplifying the analysis problem. For example, power grid wires comprise of metal of a given thickness and width. And power buses are always drawn out differentially for any high-frequency or broadband supply design. Most electromagnetic interaction of power bus wires is limited to being between the true and complement wires of a power bus pair. These aspects translate to power buses being represented as transmission lines, with frequency dependent inductance, resistance and capacitance captured during the input of the power grid into the analysis schematic. Such representation simplifies a long power bus or 3-D power grid that may consist of a very large number of polygons into a single, simple transmission plane with a single equation describing the relationship of charge and voltage along the structure.
A tool, π-fp [2] developed by the authors of this article, goes farther in its representation of the power grid, functional blocks, on- and off-chip decoupling capacitances and the entire power delivery stack. This is done through the fusing of the entire power grid into a single surface through a patent-pending 'effective current density' or ECD modeling method [3] that eliminates the specific construction of the grid from determining analysis complexity. In so representing the power grid, a distributed representation of the current consumption of any functional block, spread out within the area it occupies as it is in reality, is facilitated, as is the capture of on-chip decoupling capacitance as a distributed capacitance array.
These innovations bring the analysis to being very close to true conditions within a chip, providing a comprehensive, accurate view of noise and power integrity for the chip floor plan. Such capability, combined with an order of magnitude faster analysis speed for the entire power delivery stack, allows floor plan designers to bring the roof down, optimize supply voltage to the lowest possible level, thereby achieving the best low-power design feasible. With the ability to inspect noise distribution across the chip area and over time, designers can also make trade-offs between power integrity and low power, ensuring that their floor plans are such that critical paths in the chip are well protected from supply transients.
Advanced analysis: does capacitance really reduce noise?
In the nanoscale regime, where gate leakage is high and chip area is scarce, optimal use of on-die capacitance in reducing or deflecting noise is critical. Incorrectly configured capacitance arrangements can actually amplify noise in nanoscale SoC's. To investigate such effects, a tool that explores the electromagnetic, wave nature of on-chip noise is essential.
2. A plot of noise propagation and interaction with a CAP array.
Figure 2 shows a time dependent solution to a grid equation derived using the effective current density method (ECD, [2]). The plot shows the differential noise distribution across a 9mm x 7mm integrated circuit. Noise is injected into the power grid from the rectangular load current block at the bottom center of the image (100mA - pulse width 100ps). This noise propagates out from the noise source into a region containing distributed decoupling capacitance (5nF/cm2).
A lens shaped region is defined in the middle of the IC. This region contains additional capacitance. The electromagnetic wave velocity is slowed in this region (wave speed in a transmission line is given by v~=1/sqrt(LC) where L and C are inductance and capacitance per unit length).
The capacitance array (objects 1 through 7 in the picture) is seen to 'focus' the noise wave emanating from the load current block onto a region above it, creating a transient region of high noise in an area supposedly 'shielded' by the added capacitance. This effect seen through a 'true-EM' simulation is very similar to another more commonly observed effect, that of focusing of light through an optical lens.
This simulated solution illustrates how additional capacitance added to a power grid can result in both noise suppression and noise amplification in different parts of an IC. This is in stark contrast to the effect of decoupling capacitance in a low frequency system where any additional capacitance results in noise suppression only. Such systems are dominated by RC delay and rapid wave amplitude attenuation. High speed systems such as those in the nanoscale regime are dominated by transmission plane and LC resonance behavior that result in complex, difficult to predict, noise distributions.
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