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A decade ago, the call of the times was for solutions to address the "Power Wall", at least at leading microprocessor institutions. Conferences discussed looming challenges with supply currents exceeding 1000's of amperes, and temperatures exceeding, what was it, nuclear nozzles, or surfaces of galactic stars, and academia as well as niche industrial efforts rushed after cryogenic or microfluidic cooling systems as well as designs approaching electrical power stations on a chip. Today, power consumption is the single dominant design constraint for integrated circuits, but less noticed, and even less respected is power integrity despite its undeniable role in determining power and energy consumption. Most of us notice that if we dim the lights in our entertainment rooms too much, sharp changes in brightness of our television screens hurt our eyes. Our attempt to reduce lighting energy consumption therefore depends directly upon the level of 'light noise' we encounter. The very same is true for IC's; minimization of energy through supply voltage reduction, the most fundamental approach, depends directly upon power grid noise, or power integrity [1]. As discussed ahead, power integrity is the next dominant challenge, the call of the present for SoC's and SiP's, as power and energy continue to be dominant design constraints.
What is Power Integrity?
In simple terms, it is how close to the ideal a given power supply is, depending upon its nature. For the supply to our homes, it is amplitude and frequency, and how steady they remain despite loading and load-shedding occurring nearby. All of us may have noticed lights dimming when a large air-conditioner or refrigerator compressor kicks in; that is a degradation in power integrity.
Integrated circuits are not much different, though they typically use DC supplies of a few volts down to a volt. Power integrity for IC's is understood through knowing the droops and overshoots produced in this constant potential as parts of the IC switch on or off, or ramp up and ramp down their function. For good power integrity, it is important that these droops and overshoots, or transient (and static) changes in the value of the supply voltage differential be kept within a small fraction, say 5%, of the supply nominal, which maintains predictable performance in the integrated circuit.
The dominant components of variation in supply voltage differential in IC power grids are I*R Drop and L*di/dt, though other noise components may at times dominate, such as propagated and reflected noise as well as resonance. Analysis tools in the EDA industry today employ variations of the I*R Drop methodology to analyze voltage reduction in various sections of an integrated circuit. The relative significance of power integrity noise components is changing rapidly as scaling continues, primarily because most integrated circuits today function through binary computation involving circuits switching currents, and do so in synchrony with clock signals. As we head deeper into nanoscale processes, these switching speeds continue to increase rapidly, correspondingly increasing on-chip di/dt, and it is now imperative that we inspect 'total power integrity' including L*di/dt and other electromagnetic effects rather than just I*R Drop or its derivatives.
Loop Inductance, L*di/dt, and the impact of scaling
In studies conducted about 7 years ago, published in a technology journal as 'Emerging Directions for Packaging Technologies' [4] in its Power Delivery section, I was able to demonstrate an impractical burden placed upon support devices such as package capacitors as processors scaled inexorably. Power integrity studies showed then that the loop inductance from package capacitors into a processor device needs to scale by between the 3rd and the 5th exponent of the process scaling factor in order to maintain the same power integrity in a scaled process as in the previous generation. Loop inductance, in this instance, determined delay in response from a package capacitor to a transient charge demand by the processor, and a corresponding voltage droop in processor supply voltage.
In similar fashion, on-chip loop inductances determine the delay in response from charge stored in regions of the chip or its package to regions demanding transient charge, such as functional blocks that are switched on rapidly, or a bank of registers, flip-flops or large numbers of logic gates clocked simultaneously. A loop inductance L, in combination with a rate of rise of current, di/dt, also produces a voltage droop given by L*di/dt that adds to any instantaneous voltage drop due to wire resistance in the power distribution network. It is instructive to go through an exercise to determine how scaling impacts L*di/dt droop (noise) in successive generations. To do so, we will make a few assumptions, based on current industry trends, regarding scaling and its benefits and consequences:
- Capacitance-per-unit-area, Ca, scales by
 which is roughly (1/0.7), where 0.7 is the typical fabrication process generation scaling factor (95nm to 65, 45, 32 etc.),
- Operating voltage scales by
 which reduces it only by about 16%,
- Frequency scales by which provides a 40% improvement,
- Chip area scales by
 , reducing only by 30% rather than 50%, which indicates additional circuits integrated for improved performance in the scaled process.
With the above assumptions, called 'Roots of Two Scaling' for reference, one can deduce that active power, given by the equation αCV2ƒ remains the same in the scaled process generation as in the prior generation, assuming remains the same. In this scaling scenario, silicon area is reduced, thus reducing cost, and frequency and integration are increased, thereby increasing performance, while power penalty remains same (we assume better leakage control techniques maintain leakage power the same), maintaining the economic benefits to be accrued from following Moore's Law.
- Given above scaling, the average active current scales by the inverse of the scaling for voltage, since power remains the same, or by
 .
- Since frequency scales by , di/dt scales by* .
- Also, since the chip area scales by , each side (assume a square chip) scales by .
- Given the smaller dimension per side, and assuming that power buses are drawn with the same width and spacing (occupying roughly the same percentage of metal resources in the scaled process generation), the number of parallel buses per side reduce by a factor of , or the effective inductance increases by.
Multiplying L and di/dt in the scaled process generation for this chip, we get:
- L*di/dt scales as
 or by a factor of 2.
These calculations are obviously highly simplified and the scaling factors by no means accurate, but the trend surely is. As we scale to finer process geometries, switching edge rates are faster, while devices are smaller and operating voltages lower in order to save on active and leakage energy consumption. Though power consumption may remain the same, or may even reduce, faster processes demand faster transfer of charge or higher currents through lesser available resources such as power metal and from lesser capacitance, leading to higher voltage droops.
L*di/dt noise, as seen in this simple derivation, is doubling in every scaled process generation, mirroring the burden placed upon support components by scaling as detailed in [4] despite constant-power scaling. Assume, for example, L*di/dt or inductive noise contributions to power network noise to be of the order of 9mv in the 180nm generation. Following the derivation trend, the 45nm node could see 16 times as much inductive noise, or about 144mv, which can be about 15% of the supply voltage differential, or 3X the allowed maximum noise. Academic research has shown a similar trend in quadratic increase of inductive noise with rise times [2] determined with careful and complex PEEC modeling of power distribution grids. I*R Drop tools completely miss this aspect of power integrity; any light at the end of this methodology tunnel is clearly the headlight of the L*di/dt train rushing exponentially towards us all.
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