The need to address power during manufacturing test

Power Consumption during Functional Mode vs. Test Mode

Several studies show that test mode power consumption in deep submicron devices can be several times higher than power consumption at functional modes. While typical test mode power consumption limits are usually around 2X functional power, in fact power consumption can be much higher, for a variety of reasons.

For instance, simultaneous testing of multiple modules is sometimes implemented to reduce tester costs -- even though in functional operation, it may be impossible to operate more than a few modules at a time. Switching within logic circuits during scan shift, and high switching rates during scan shift/capture, also produces higher power consumption during test. Similarly, fast at-speed capture pulses in transition test patterns can cause unwanted peak power spikes, leading to IR-drop issues. Finally, increasing the frequency of scan shift cycle to reduce test time can also cause unduly high power consumption at the tester.

Other departures from functional power consumption levels result from field test requirements for worst-case functional power; burn-in testing; and high-voltage testing of devices, all of which result in elevated voltages and temperatures, potentially creating negative impacts on both the test outcome and the device's low power circuitry.

Handling Excessive Power Consumption during Scan Test

In any methodology to reduce test power, the test coverage impact must be low and there should be minimum impact on ATPG tools and flows. Similarly, the test data volume and test time should not be significantly impacted either. Also, too much reduction of test mode power consumption may impact test quality by not stressing the circuit sufficiently, so that's to be avoided as well. Finally, the strategy must not impact physical design care-abouts, such as area, power, and functional timing, and it must not place development time at risk.

DFT Techniques: Q-output Gating and Scan Partitioning

Two examples of common power management techniques include Q-output gating and low-power scan partitioning.

In Q-output gating, during scan shift the switching activity in the combinational circuit can be minimized if gating logic is intelligently inserted at Q-outputs of key scan flops. The gating logic is controlled by a test signal, and is disabled during capture cycle and normal functional mode. During scan shift operation, Q-output gating mitigates propagation of switching activity through scan flip-flops to combinational logic. It's important to only gate registers that have high impact on scan-mode power reduction but minimal impact on critical timing paths in the design.

Scan partitioning is another DFT technique to manage test power. By inserting DFT logic, each scan chain is split up into multiple segments such that when test data is loaded/unloaded from one scan segment, the clocks to all the other segments are gated off to reduce power. Low-power scan partitioning has been implemented in commercial designs such as the CELL processor used in gaming systems.

Yet another related DFT technique for reducing test power includes data gating, where scan chains that are in a region of the design not currently being tested can be loaded with a constant value. Test points need to be inserted so that the idle chains are loaded with zeros to reduce switching activity, while the active chains are loaded with values from the tester.

DFT Technique: Inhibiting Output Drivers

Output drivers typically consume many times more power when switching than internal logic. Avoiding output driver switching can be important to managing average power, instantaneous power, and IR drop. The main idea is to keep all 3-state output drivers in the inhibited (high-Z) state during any test mode clock pulse. This applies to capture and scan shift clocks. This can be accomplished by using one or more control inputs that force the drivers to Z when signals are asserted. During scan shift all drivers should be inhibited except active scan output pins.

Often chip manufacturers develop chips containing thousands of signal I/O pins, most of which may be output or bidirectional. With so many 3-state outputs, you want to avoid simultaneous switching even when not pulsing a clock. When a large number of drivers are inhibited by a single control signal, this causes too many drivers to turn ON with corresponding spikes in current demand and IR drops. You can avoid such conditions by using more than one driver inhibit control signal. It is also effective to have the control signals run through a staggered delay. The careful use of DFT insertion and ATPG of such driver inhibit controls is an important consideration in any low-power test methodology.

ATPG Technique: Power Aware Test Pattern Generation

Looking beyond DFT methods, commercial ATPG tools now consider power-aware test pattern generation. ATPG patterns typically target a fault or group of faults when a pattern is generated. Patterns without conflicting control states can be merged into a single pattern. This is called pattern compaction. When compaction is complete, generally less than 3% of the control points contain values that define the test for the targeted faults. These defined control points are called care bits. The remaining control points (called don't-care bits) can be filled with default random logic values. These random values serendipitously test faults not targeted by the pattern.

This random value filling of don't-care bits results in about 50% of design scan flops switching during scan. Commercial ATPG tools offer a technique for power management with the pattern generation capability of adjusting the default random fill. The repeat-fill approach repeats the last care bit until another care bit is encountered, which ensures that switching during a scan shift load is significantly reduced. Equivalent fault coverage is achieved using either method.

For example, if the ATPG pattern is 0XXXX110XXXX11XXXX11 where the X's represent dont-care bits then random-fill may lead to a final pattern such as 01010110101011010111 while repeat-fill will lead to 01111110111111111111. The random-fill option has 15 bit flips while the repeat-fill option has only 3 bit flips leading to significantly lower toggle rate during scan chain shift. To avoid too much switching reduction, another option is to add random bits to increase switching before using repeat-fill on the rest of the bits. Some ATPG tools provide greater automated control over patterns to avoid under-stressing the IC.

Table 1: An example of switching power during conventional scan versus low power scan using test mode power management techniques in various steps throughout the IC design and ATPG flows.

Power Component Testing

To address power during functional operation, architectural-level power management techniques including multiple supply voltages (MSV) and power shutoff (PSO) are becoming more widely implemented. Such techniques can provide up to 80 percent dynamic power reduction, and several orders of magnitude reduction in leakage power. These designs have multiple power modes such that different regions (also called domains) of the design are powered on in each power mode.

From a DFT perspective, when test structures such as internal scan chains, test compression, memory BIST etc., are inserted into such designs, they must be operational in the target power modes. When testing the chip in a test mode corresponding to a power mode, the test structures and the controller macro that enables and maintains the different power modes should be fully controllable from the tester.

Many conventional test solutions 'override' these low power features and test with all domains powered ON. In a power-aware test methodology, the design's functional power modes are mapped to test modes for ATPG. The mapping must be such that we include at least one instance of each power domain in an "on" condition which permits targeting active logic faults while testing the power domain isolation logic and "on condition" verification. Similarly, we also need to include at least one instance of each power domain in an "off" condition for verification and test generation purposes.

Another consideration is testing power component structures, including power controllers, power switches, and state retention (SR) flops; structures used for functional power management. During manufacturing test, defects in these low power components must be accurately modeled and tested. For example, conventional structural testing is not sufficient for testing logic that supports power shutoff and mode transitions because conventional ATPG and fault models do not sufficiently account for logic being powered down. For example, after powering down the domain containing a SR cell, it is possible the SR may be functioning incorrectly by not retaining the state it was loaded with initially. Power-component-aware testing is now supported by commercial DFT and ATPG tools.

Conclusion

The potential impacts of power consumption during manufacturing test can no longer be ignored. A number of IC design teams have shown that good engineering planning, concurrency, and adoption of power-aware DFT, ATPG, and Sign-off tools can mitigate power issues during test while testing the low-power architecture and components. This article highlighted several DFT and ATPG techniques that have moved from novelty to accepted practice. With the rapid proliferation of low power electronics, it is clear that more innovations, tools, and best practices in DFT and ATPG can be anticipated down the road.

About the Authors:

Anis Uzzaman is a Sr. Product Engineering manager at the Front End Design Group of Cadence Design Systems, Inc. Anis has a B. Eng degree in Electrical Engineering from Tokyo Institute of Technology, Japan and an MS degree from Oklahoma State University.

Patrick Gallagher is an architect for the Front End Design Group of Cadence. Patrick is a graduate of Rochester Institute of Technology (RIT) in Rochester, NY.

Edward Malloy is a Product Marketing Manager for the Front End Design Group of Cadence. Ed holds a BSEE, JD, and MBA.