Introduction
As more complex, mixed signal System on Chip (SoC) designs continue to stress verification methodologies and schedules, designers need new approaches in solving today's test challenges. Mixed signal verification presents a unique challenge as the analog portion of the design requires highly accurate, and time consuming, analog simulation (Spice for example).
Furthermore, without a digital representation of the analog design, full digital regression simulations are not possible for the SoC. This is insufficient for verifying connectivity and basic functionality of the integrated SoC at the system level. Intrinsix recently evaluated the Cadence Design Systems' Real Number Modeling (RNM) methodology as a possible solution for achieving efficient mixed signal verification.
Intrinsix is a leading supplier of sigma-delta data converter IP. Many of our customers are using Sigma-Delta Modulator (SDM) technology to develop sensors for automotive, consumer and aerospace applications. All of these designs require similar signal processing. Figure 1 shows a block diagram of typical "Big-D, Little-A", mixed signal SoC data converter IP design.
Figure 1: Sigma-Delta Data Converter IP
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Currently, our analog designers have a well-defined methodology that uses MATLAB Simulink and the Cadence Virtuoso Accelerated Parallel Simulator, an important component of its Multi-Mode Simulation suite (MMSIM). The digital verification team creates a SystemVerilog environment within the Cadence Incisive functional verification platform. Each design block is verified standalone. A full chip simulation can be run within the MMSIM simulator, but the SystemVerilog, metric driven, functional verification methodology cannot be supported by MMSIM. What has been missing is an efficient simulation environment that provides the features of a SystemVerilog-based digital simulation environment for a mixed signal design.
Cadence has introduced a methodology to address this need, Real Number Modeling. Real Number Modeling (RNM) defines a new wired real (wreal) data type net concept, with Verilog-AMS, as a solution for modeling analog designs in the mixed signal verification environment. The RNM methodology has allowed Intrinsix to apply the rigid methodology of a digital verification flow (assertions and functional coverage) to a mixed signal design. For Intrinsix, target applications for the wreal solutions are top level SoCs with small to moderate analog in the design (BigD/LittleA). In this paper, we will present a mixed-signal SoC design as an example to illustrate how the wreal solution is applied to the problem.
The SoC data-converter example
Figure 2: Sigma Delta Converter
Click on image to enlarge. |
Figure 2 illustrates the SDM analog design used in the Data Converter SoC. Analog simulations are accurate but very slow, and do not support a SystemVerilog flow. This prevents regression testing for top-level system verification. During the early testing phase of this design, analog simulations were run using Spice and Verilog-A models. A sine wave with preset amplitude and frequency was driven in to produce a known good digital output data stream. The output data stream was captured in file. This file was later used as input stimulus to the digital sub-system of the SoC. This piece meal verification approach becomes inefficient as the design complexity and size increases. Therefore, a faster and more integrated methodology was devised.
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