|
|
Most Popular Articles |
|
|
Rank |
|
Title |
|
Author/Company |
|
Date/Type |
| |
1
|
|
Understanding Clock Domain Crossing Issues
|
|
Saurabh Verma, Ashima S. Dabare, Atrenta
| |
Dec 24, 2007
|
| |
2
|
|
FPGA design methods for fast turn around
|
|
Angela Sutton
| |
Mar 04, 2010
|
| |
3
|
|
The Different Types of UPS Systems
|
|
American Power Conversion Corp.
| |
Oct 28, 2004
|
| |
4
|
|
A silicon-proven interoperable PDK
|
|
Rich Morse, SpringSoft, and Tom Quan, TSMC
| |
Mar 05, 2010
|
| |
5
|
|
High-level synthesis, verification and language
|
|
John Sanguinetti, CTO of Forte Design Systems Inc.
| |
Feb 22, 2010
|
| |
6
|
|
Complex SoC Testing with a Core-Based DFT Strategy
|
|
Sandeep Kaushik, Synopsys and Paul Policke, Qualcomm
| |
Feb 26, 2008
|
| |
7
|
|
Utilizing Clock-Gating Efficiency to Reduce Power
|
|
Mitch Dale, Calypto Design Systems
| |
Jan 15, 2008
|
| |
8
|
|
Simplifying PLL Design
|
|
Bob Mullen, Cadence Design Systems
| |
Feb 12, 2008
|
| |
9
|
|
How to inexpensively design an ASIC in 5 weeks
|
|
Narinder Lall
| |
Mar 02, 2010
|
| |
10
|
|
Xilinx Virtex-6 FPGA User Guide Lite
|
|
Peter Alfke, Xilinx Inc.
| |
Jul 22, 2009
|
| |
11
|
|
Embedded system virtualization for executable specifications and use case modeling
|
|
Vincent Perrier, CoFluent Design (Nantes, France)
| |
Jan 26, 2010
|
| |
12
|
|
Applying Constrained-Random Verification to Microprocessors
|
|
Jason C. Chen, Synopsys Inc.
| |
Dec 10, 2007
|
| |
13
|
|
Using OVM to reuse vital verification knowledge
|
|
Jana Richards, LSI Corp. and Dan Cohen, Mentor Graphics
| |
Jan 05, 2010
|
| |
14
|
|
Preserving The Intent Of Timing Constraints
|
|
Sridhar Gangadharan, Ramesh Dewangan, Atrenta Inc
| |
May 17, 2008
|
| |
15
|
|
Functional programming paradigm and concurrency
|
|
Aditi Athavale and PushpRaj Agrawal
| |
Mar 02, 2010
|
| |
16
|
|
Characterizing Nanometer CMOS PLLs, Sigma-Delta ADCs and AGCs
|
|
Yiqun Lin, Silicon Laboratories
| |
May 13, 2008
|
| |
17
|
|
Process Intelligent Modeling and Statistical STA improve DFM
|
|
Prashant Maniar, Amit Majumdar, Hitendra Divecha, Stratosphere Solutions, Inc., Michael Jacobs, Rahul Deokar, Cadence Design Systems
| |
Sep 11, 2007
|
| |
18
|
|
EDA 3.0: So you are an EDA startup?
|
|
Tom Kozas and Michael Sanie
| |
Mar 17, 2009
|
| |
19
|
|
Rigorous Automated Verification Yields High Quality Silicon
|
|
Henry Angulo, Asad Khan and Scott Morrison, Texas Instruments Incorporated
| |
Apr 24, 2007
|
| |
20
|
|
A Power Integrity Wall follows the Power Wall
|
|
Raj Nair, Anasim Corp.
| |
Apr 08, 2008
|
| |
21
|
|
Topology Planning and Routing
|
|
Dean Wiltshire, Mentor Graphics Corporation
| |
Jul 30, 2007
|
| |
22
|
|
Facilitating at-speed test at the register transfer level
|
|
Ralph Marlett and Kiran Vittal, Atrenta Inc.
| |
Feb 19, 2010
|
| |
23
|
|
Serial ATA and the evolution in data storage technology
|
|
Mohamed A. Salem, Mentor Graphics Corp.
| |
Apr 28, 2008
|
| |
24
|
|
Low Power Design For Analog/Mixed-Signal IP
|
|
Navraj Nandra, Synopsys
| |
Mar 04, 2008
|
| |
25
|
|
Hands-on: Get started in analog IC design and fab (Part 2 of 3)
|
|
Stephen H. Lafferty
| |
Jun 11, 2009
|
|
|
|
