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Most Popular Articles |
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Title |
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Author/Company |
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Date/Type |
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1
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Understanding Clock Domain Crossing Issues
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Saurabh Verma, Ashima S. Dabare, Atrenta
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Dec 24, 2007
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2
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BGA Breakouts and Routing
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Gabe Moretti
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Jul 21, 2008
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3
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ESL handoff: closer than you think
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Michael McNamara, Cadence Design Systems
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Jul 08, 2008
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4
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Simplifying PLL Design
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Bob Mullen, Cadence Design Systems
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Feb 12, 2008
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5
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The Different Types of UPS Systems
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American Power Conversion Corp.
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Oct 28, 2004
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6
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Utilizing Clock-Gating Efficiency to Reduce Power
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Mitch Dale, Calypto Design Systems
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Jan 15, 2008
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7
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Preserving The Intent Of Timing Constraints
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Sridhar Gangadharan, Ramesh Dewangan, Atrenta Inc
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May 17, 2008
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8
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Proportional-integral-derivative explained
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Javier Gutirrez, National Instruments
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Apr 13, 2007
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9
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Low power design for analog/mixed signal IP
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Navraj Nandra
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Jun 24, 2008
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10
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Software-Defined Radio Platforms
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Bart Van Poucke, Bruno Bougrad, and Jan Provoost, IMEC.
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Mar 24, 2008
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11
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ESL Methods for Optimizing a Multi-media Phone Chip
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Danilo Piergentili, David Coupe, NXP Semiconductors
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May 27, 2008
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12
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Accellera VHDL Standard
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Jim Lewis, SynthWorks VHDL Training
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Oct 25, 2007
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13
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A New Approach to In-System Silicon Validation and Debug
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Miron Abramovici and Paul Bradley, Dafca
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Sep 16, 2007
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14
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Bridging the Gap Between Silicon and Software Validation
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Paul Bradley, DAFCA, Inc
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Jun 06, 2008
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15
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What floorplan information is needed for synthesis
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Jack Erickson, Cadence Design Systems
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Apr 22, 2008
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16
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Low Power Design For Analog/Mixed-Signal IP
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Navraj Nandra, Synopsys
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Mar 04, 2008
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17
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Getting Back to Basics with Planning, Metrics, and Management
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Hamilton Carter, Cadence Design Systems
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Jul 13, 2007
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18
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The Great EDA Cover-up
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Brian Bailey
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Nov 26, 2007
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19
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Single Flow for Interconnecting IP
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Mike Smith and Jo Anderson; Beach Solutions Ltd
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Jun 20, 2008
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20
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Dynamic Voltage Droops & Total Power Integrity
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Raj Nair and Donald Bennett, Anasim Corp.
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May 23, 2008
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21
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PCB Tools Vendors Reference Chart
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Gabe Moretti
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Feb 14, 2008
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22
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How to build reliable FPGA memory interface controllers without writing your own RTL code!
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Adrian Cosoroaba, Xilinx
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Apr 19, 2006
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23
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Model-Based Metal Fill Optimizes Planarization and Increases Yield
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Charles Chiang, Synopsys Inc., Seiji Norimatsu, STARC, and Mitsuhiro Tomita, STARC
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Mar 22, 2007
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24
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New EDA Tools Improve Low Power Design
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Dave Allen, Atrenta
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Feb 19, 2007
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25
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Complex SoC Testing with a Core-Based DFT Strategy
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Sandeep Kaushik, Synopsys and Paul Policke, Qualcomm
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Feb 26, 2008
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