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Highest Rated Articles |
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Score |
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Title |
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Author/Company |
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Date/Type |
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5
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A Power Integrity Wall follows the Power Wall
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Raj Nair, Anasim Corp.
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Apr 08, 2008
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4.83
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Power Integrity and Energy Aware Floor Planning
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Raj Nair and Donald Bennett, Anasim Corp
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Jan 29, 2008
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4.82
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Dynamic Voltage Droops & Total Power Integrity
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Raj Nair and Donald Bennett, Anasim Corp.
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May 23, 2008
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4.75
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Characterizing Nanometer CMOS PLLs, Sigma-Delta ADCs and AGCs
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Yiqun Lin, Silicon Laboratories
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May 13, 2008
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4.71
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Rigorous Automated Verification Yields High Quality Silicon
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Henry Angulo, Asad Khan and Scott Morrison, Texas Instruments Incorporated
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Apr 24, 2007
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4.67
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Understanding Clock Domain Crossing Issues
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Saurabh Verma, Ashima S. Dabare, Atrenta
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Dec 24, 2007
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4.6
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Preserving The Intent Of Timing Constraints
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Sridhar Gangadharan, Ramesh Dewangan, Atrenta Inc
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May 17, 2008
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4.6
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Verification Platform for Complex Designs
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Amit Dua, Cadence Design Systems
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Dec 31, 2007
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4.5
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Embedded developers should embrace FPGAs
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Rob Irwin, Altium Limited
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Aug 09, 2007
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4.5
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Verifying Configurable Verification Interfaces Using OCP
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Jay Littlefield, Øystein Kolsrud, Jasper Design Automation
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May 10, 2007
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4.5
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Achieving completeness in IP functional verification
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Wolfram Buettner and Michael Siegel, OneSpin Solutions
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Feb 12, 2007
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4.44
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Signoff for Manufacturability
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Chin-Chi Teng and Rahul Deokar, Cadence Design Systems, Inc
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Oct 08, 2007
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4.44
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Getting Back to Basics with Planning, Metrics, and Management
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Hamilton Carter, Cadence Design Systems
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Jul 13, 2007
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4.42
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New EDA Tools Improve Low Power Design
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Dave Allen, Atrenta
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Feb 19, 2007
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4.4
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Achieving Certified IP Quality Efficiently
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Lorenzo di Gregorio, Infineon Technologies AG, Carlo del Giglio, Michael Siegel, OneSpin Solutions GmbH
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May 29, 2007
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4.4
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Practical Approaches to Deployment of SystemVerilog Assertions
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Faisal Haque, Jon Michelson
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Apr 03, 2007
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4.4
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Metrics measure IC design productivity
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Michael Solka, Synopsys, Inc.
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Oct 16, 2006
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4.38
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Practical Applications of Statistical Static Timing Analysis
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Parveen Khurana and Michael Jacobs, Cadence Design Systems, Inc.
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Dec 18, 2006
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4.33
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Total Power Optimization in RTL-to-GDSII Implementation Flow
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Arvind Narayanan, Magma Design Automation
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Mar 12, 2007
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4.33
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How to architect, design, implement, and verify low-power digital integrated circuits
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Andy Eliopoulos, Pinhong Chen, and Dr. Qi Wang, Cadence Design Systems
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Jan 29, 2007
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4.31
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Accurate Thermal Analysis of Chip/Package Systems
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Ting-Yuan Wang and Margaret Schmitt, Apache Design Solutions
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Mar 15, 2007
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4.3
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Multi-language Functional Verification Coverage for Multi-site Projects
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Apurva Kalia, Cadence Design Systems
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Feb 18, 2008
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4.29
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Model-Based Metal Fill Optimizes Planarization and Increases Yield
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Charles Chiang, Synopsys Inc., Seiji Norimatsu, STARC, and Mitsuhiro Tomita, STARC
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Mar 22, 2007
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4.22
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The Great EDA Cover-up
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Brian Bailey
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Nov 26, 2007
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4.2
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ESL Methods for Optimizing a Multi-media Phone Chip
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Danilo Piergentili, David Coupe, NXP Semiconductors
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May 27, 2008
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