EDA News | News Source for EDA Tools, DFM, ESL, Verification, Chip, and System Design

Michael Fister Resigns -- Interim Office of the Chief Executive Created
Cadence has announced that its Board of Directors has formed an Interim Office of the Chief Executive to oversee the day-to-day running of the company's operations, effective immediately. The formation of the Interim Office of the Chief Executive followed Michael Fister's resignation as President, Chief Executive Officer and a director of the company.

LogicVision fires three execs
LogicVision Inc., a provider of semiconductor built-in-self-test and diagnostic solutions, said that three of its executive officers will be leaving in an effort to cut costs.

Renesas COO: Economy to have 'severe' impact on ICs
Japan's Renesas Technology Corp. said that it aggressively plans to boost its international business and expand its microcontroller share, but shaky economic conditions could delay its lofty goals.

Custom Lithography Addresses 22-Nanometer Semiconductor Manufacturing
Cadence announced that it has developed software that optimizes custom lithographic source illumination, a new capability in its integrated source mask optimization (SMO) technology family for IC manufacturing at 22 nanometers and beyond.

EDA revenue fall accelerated in Q2, group reports
The EDA Consortium Market Statistics Service announced Friday (Oct. 10) that the electronic design automation industry revenue for Q2 2008 declined 3.7 percent to $1357.4 million, compared to $1408.8 million in Q2 2007. Sales were slightly down on $1350.7 billion recorded in Q1 2008, which themselves had been down 1.2 percent on Q1 2007.

Synopsys CEO: Five ways to cut design costs
Photomask complexity is outstripping the compute power in today's mask shops, prompting the need for new technologies like computational lithography and other schemes, according to the top executive at Synopsys Inc.

Ensuring the Quality of Verification: Coverage vs. Qualification
EDA needs functional qualification, a new category of EDA product. The technology is fundamentally different from existing coverage technologies. The implications for the verification profession could be radical.

Magma to restructure operations, reduce workforce
EDA vendor Magma Design Automation plans to restructure its operations and lay off an unspecified number of workers, the company said.

Measuring Quality in Semiconductor IP
The industry would benefit from a standard method to measure IP quality.

IBM Announces New Standards Policy
IBM has announced a new corporate policy guiding its partecipation in standards making bodies.

Viewpoint: Innovation is being delivered by plug-and-play start-up solutions
For an EDA start-up company to add value to today's semiconductor designers, the start-up company must provide additional value above and beyond the algorithms and solutions available within these large, single vendor product portfolios.

EDA firms collaborate to optimise analog parametric yield
Grenoble based Infiniscale is working with Mentor Graphics and shared customer, STMicroelectronics, to provide parametric yield optimisation to guarantee sizing and improve yields in sub-90nm designs.

ARC moves engineering jobs to Russia, India
ARC International plc (St. Albans, England) has said it plans to reorganize its operations. A key element in the plan is to move some product development to engineering centers in Russia and India, the company said.

US engineering services firm opens in Armenia
Utah-based Cambric, a provider of outsourced engineering services, has opened operations in Yerevan, Armenia.

Agilent Technologies enters ESL Market
Agilent Technologies has introduced SystemVue 2008, a new electronic design automation (EDA) platform for electronic system-level (ESL) design.

About the EDA DesignLine News Section
About the EDA DesignLine News Section News/analysis source for engineers tapping EDA tools/techniques for issues such as chip design, SoC architectures, electronic system level (ESL) design, DFM/DFY design, functional/physical verification, FPGA, PLD, analog, and mixed-signal design.