EDA News | News Source for EDA Tools, DFM, ESL, Verification, Chip, and System Design

Evatronix to host technical 8051 and USB seminars in Asia
For those who use digital IP in the chip design process and wish to get faster to market with their SoC, Evatronix SA (Bielsko-Biala/Poland) has scheduled two free technical seminars on two popular IP technologies in the semiconductor industry —8051 and USB— in Beijing, China, and Hsinchu, Taiwan.

Viewpoint: Your future is programmable
The state of the electronics industry today, and certainly in the future, directly challenges that traditional view of technology-focused product design evolution.

Stratix IV passes Interlaken device interoperability testing
Altera said its Stratix IV FPGAs passed the Interlaken Alliance's device interoperability testing, certifying that its FPGAs interface with third-party components using the Interlaken protocol.

FPGA startup: Process tech eases ASIC migration
A little more than a week after long-simmering programmable logic startup Tabula emerged from stealth mode, Tier Logic stepped into the light to offer the first details about its technology, which employs a novel processing change to build FPGA and ASIC products on a single die.

Magma releases alternative to Monte Carlo analysis
Magma Design Automation Inc. claimed its FineSim Fast Monte Carlo statistical simulation method delivers superior accuracy and up to 100 times speed improvement over traditional Monte Carlo analysis.

Magma readies static timing analysis platform
Magma Design Automation Inc. has introduced the Tekton timing analysis platform that is claimed to deliver fast multi-scenario analysis on a single CPU.

Getting disciplined about embedded software development: Part 3 - The value of postmortems
Here's a guide from Jack Ganssle on doing software development in a disciplined way to reduce both errors and the time it takes to complete a project. Part 3: The value of postmortems

IMEC, Synopsys to boost 3D stacked IC development
IMEC (Leuven, Belgium) said it is using Synopsys' TCAD simulation tools for characterizing and optimizing the reliability and electrical performance of through-silicon vias (TSVs).

Visitors up 16% at Embedded World
The organizers of the Embedded World exhibition and conference 2010 have reported it ended on a very successful note with a record number of visitors and exhibitors, as confirmed by 730 international exhibiting companies, 4 per cent up on last year, and 18,350 trade visitors up 16 per cent.

Jim Hogan joins GateRocket advisory board
FPGA verification and debug software vendor GateRocket Inc. announced veteran EDA investor Jim Hogan has joined its advisory board.

Getting disciplined about embedded software development: Part 2 - The Seven Step Plan
Here's a guide from Jack Ganssle on doing software development in a disciplined way to reduce both errors and the time it takes to complete a project. Part 2: The Seven Step Plan.

Getting disciplined about embedded software development: Part 1 - Any idiot can write code
Here's a guide from Jack Ganssle on doing software development in a disciplined way to reduce both errors and the time it takes to complete a project. Part 1: Any idiot can write code.

Carbon readies virtual models for ARM Mali GPUs
Carbon Design Systems (Acton, Mass.) has released virtual models for ARM Mali Graphic Processor Units (GPUs).

IMEC, Altos team on chip design, prototyping services
IMEC (Leuven, Belgium) and Altos Design Automation Inc. (San Jose, Calif.) have joined forces to provide re-characterization of standard foundry or library vendor libraries including core and IO cells at different process, temperatures and/or voltages.

Decompiling the ARM architecture code
At UBM TechInsights we are often tasked with proving patent infringement of a software algorithm as part of our IP Management Services. Our example algorithm is based on the ARM architecture.

About the EDA DesignLine News Section
About the EDA DesignLine News Section News/analysis source for engineers tapping EDA tools/techniques for issues such as chip design, SoC architectures, electronic system level (ESL) design, DFM/DFY design, functional/physical verification, FPGA, PLD, analog, and mixed-signal design.