SAN JOSE, Calif. -- Silicon foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) continues to move down the analog and mixed-signal path.
TSMC (Hsinchu) has released an enhanced version of its 0.13-micron foundry process that includes analog and power management features.
The 0.13-micron process--along with the 0.11-micron half-node offering--now includes a slim standard cell as well as a separate LDMOS (5V-20V) on RF platform technology to enable analog and power management applications.
The slim platform I/O area achieves a 30 percent reduction and SRAM bit cells demonstrate a 25 percent reduction when compared with traditional offerings.
The slim cell process is available in the third quarter this year, while the LDMOS on RF platforms will be available in Q4 this year.
Digital chip designers are integrating more analog/mixed-signal functions on the same chip.
The foundries are jumping on the trend. Last year, for example, TSMC joined the Interoperable PDK Libraries industry alliance. The IPL group, which includes Magma, Mentor, Synopsys and other tool and intellectual- property vendors, is pushing for a standard foundry process design kit (PDK). If and when this PDK technology hits the commercial market, it will function as an "interoperable" reference flow for analog and custom IC design, backers say.
Seeking to accelerate the product development process, TSMC recently rolled out a one-two punch in the arena: It has unveiled a mixed-signal/RF design kit as well as a foundry-specific integrated sign-off flow.
