Newsletter

EDA DesignLine  >  Product Center
Products

IPextreme rolls cJTAG IP core
IPextreme Inc. has announced the availability of the industry's first synthesizable IP core that implements the upcoming IEEE 1149.7 standard, which will be ratified in early 2009.

Magma rolls analog mixed-signal design platform
Magma Design Automation introduced Titan Analog Migration, a model-based design platform said to dramatically reduce design porting time of analog mixed-signal circuit designs.

Cadence tackles issues in IC package/SiP design
The announced release of SPB 16.2, due in November of this year, from Cadence Design Systems, focuses on addressing current and emerging chip package design challenges.

Cadence introduces constraint-driven HDI design flow for PCB
Cadence Design Systems, Inc. announced improvements to the Cadence Allegro and OrCAD families of products.

Imperas announces agreement with MIPS Technologies
Imperas and MIPS agree to collaborate on a family of verified processor models.

Agilent Technologies announces integrated simulation solution
Agilent Technologies Inc. has introduced an integrated design flow solution that includes full 3D EM (electromagnetic) simulation for RF Module Design.

NI updates LabVIEW for multicore and wireless design
LabVIEW version 8.6 from National Instruments Corp. (Austin, Texas) adds techniques to improve design with multicore processors, field-programmable gate arrays (FPGAs) and wireless communication.

AWR adds high-frequency filter design to Microwave Office
AWR works with its partner, Nuhertz Technologies, to add filter synthesis and analysis to its high-frequency design suite.

Mentor Graphics delivers CHS 2008.1
The 2008.1 release of Mentor's CHS design software provides electrical simulation functionality inherently within the core Capital Logic and Capital Integrator tools.

Synopsys announces synthesizable PowerPC cores
Synopsys, Inc.has developed fully synthesizable implementations of the IBM PowerPC 460 and cache configurable PowerPC 405.

Synopsys broadens DesignWare SATA solution with Device IP
Synopsys, Inc. announced the availability of the DesignWare SATA Device IP.

Cadence introduces C-to-Silicon Compiler
Cadence Design Systems, Inc. introduced C-to-Silicon Compiler, a high-level synthesis product supporting the creation and re-use of system-on-chip IP.

Mentor Accelerates Verification of PCI Express Applications
Mentor Graphics announced its high-performance platform to accelerate the verification of PCI Express products.

Board Interchanger for Concurrent Mechanical and PCB Design
Board Interchangeris a tool from Zuken for concurrent mechanical and PCB design.

New Publishing And Version Control Features From Altium
Altium has added project management and design data publishing capabilities to its unified electronic design solution.



EDA PRODUCTS ARCHIVE

September 2008 EDA Products
August 2008 EDA Products
July 2008 EDA Products
June 2008 EDA Products
May 2008 EDA Products
April 2008 EDA Products
March 2008 EDA Products
February 2008 EDA Products

About the EDA DesignLine Products Section
About the EDA DesignLine Products Section The EDA DesignLine product section highlights the latest products in areas such as DFM, DFY, verification, simulation, HDL synthesis, interconnect design, place and route, signal integrity, FPGA synthesis, intellectual property, and more.

Resource Links

 Featured Jobs
T-Mobile seeking Manager 3, Engineering in Snoqualmie, WA

Cirrus Logic seeking Digital IC Design Engineer in Austin, TX

SanDisk seeking Sr Manager, ASIC Design in Milpitas, CA

Exceptional Innovation seeking Electrical Engineer in Westerville, OH

Center for Nanoscale Sci and Tech seeking Operations Mangr in Gaithersburg, MD

More jobs on EETimesCareers
 Sponsor
 CAREER CENTER
Ready to take that job and shove it?
SEARCH JOBS:

 SPONSOR

 RECENT JOB POSTINGS
For more great jobs, career related news, features and services, please visit EETimes' Career Center.


   
Resource Links